The present invention relates to a signal transfer system having a plurality of signal input-output sections that are connected with each other in a cascade manner, a display panel drive apparatus, and a display apparatus using such a display panel drive apparatus, the respective system and apparatuses being provided in a drive apparatus of a liquid crystal display apparatus, for example.
Recently, a liquid crystal display apparatus of an active matrix type has been widely used as a display apparatus for a personal computer of such as a desk top type or a notebook type or as every kind of monitor. The liquid crystal display apparatus of an active matrix type is provided with an active matrix substrate on which a plurality of pixels electrodes are provided in a matrix manner, an opposing substrate on which an opposing electrode is provided, and a liquid crystal layer provided between the active matrix substrate and the opposing substrate.
The active matrix substrate is provided with switching devices such as TFTs (Thin Film Transistors) for selectively driving the pixel electrodes. The switching devices are connected with the respective pixel electrodes. The TFT has a gate electrode that is connected with a gate bus line and a source electrode that is connected with a source bus line. The gate bus line and the source bus line are provided so as to extend orthogonal to each other around the respective pixel electrodes that are provided in a matrix manner. When the gate signal is inputted via the gate bus line, the TFT is driven and controlled, and concurrently, a data signal (display signal) is inputted into the pixel electrode via the TFT during the driving of the TFT in response to a signal sent via the source bus line. This allows that an electric field is generated between the pixel electrode and the opposing electrode. The electric field causes the alignment state to change so as to display the image.
Each source bus line is connected with the source driver which outputs the data signal to each source bus line. The source drivers are provided in accordance with the number of the source bus lines. Each source driver receives the data signal to be sent to the source bus line associated with the source driver via a timing controller.
The data transfer to the source driver is carried out in response to the signals such as a start pulse input signal SPin, a data signal DATA, and a start pulse output signal SPout. FIG. 17 is a time chart showing the respective signals in the nth source driver n and the (n+1)th source driver n+1. This example deals with the case where each source driver has 300 outputs. When it is assumed that the data of each color component of R, G, and B for 1 block are fetched, it appears that the sampling of the data corresponding to 100 clocks is carried out with respect to a single source driver.
After receiving the start pulse input signal SPin, each source driver starts to carry out the data sampling in response to the next clock. When the data sampling corresponding to 100 clocks is completed, the start pulse output signal SPout is sent to the source driver of the next stage. The start pulse output signal SPout is sent to the source driver of the next stage as a start pulse input signal SPin. This allows the source driver of the next stage to carry out a data sampling in a manner similar to the above-described procedure.
As to the entire liquid crystal panel, in the case of SVGA having 800xc3x97600 pixels, 8(800÷100(clocks)) source drivers are connected with each other in a cascade manner. FIG. 18 is an explanatory diagram showing the schematic connecting state of the source drivers STAB1 through STAB8. As shown in FIG. 18, the data signal DATA and the latch strobe signal LS are sent to the respective source drivers STAB1 through STAB8 in parallel. The start pulse input signal SPin is sent to the source driver STAB1. The source driver STAB2 and its succeeding source drivers receive the start pulse SPout from the source driver of the previous stage as the start pulse input signal SPin.
In the case where the data samplings of the source drivers STAB1 through STAB8 are completed in the above-described manner, when the latch strobe signal is sent to the respective source drivers STAB1 through STAB8, an analog voltage corresponding to all the sampling data that correspond to 1 line is outputted from the output terminals of the respective source drivers STAB1 through STAB8. A voltage corresponding to the data signal is applied to each of the pixel electrodes on the line that has been selected by the gate signal.
In the timing chart shown in FIG. 17, the operating frequency of the start pulse input signal SPin the data signal DATA and the start pulse output signal SPout is coincident with the clock frequency fck. For example, in the case of SVGA, the clock frequency fck is equal to 40 MHz (clock period Tck=1/fck=25(ns)) according to the VESA (The Video Electronics Standards Association) standard, while in the case of XGA, the clock frequency fck is equal to 65 MHz (clock period Tck=15.38(ns)).
FIG. 19 shows the timing charts of the clock signal and the data signal DATA, respectively. Note that it is assumed that the data sampling is carried out in synchronization with the rising (see time Tu in FIG. 19) of the clock signal. During the time period between the time that is 1.5(ns) to the time Tu and the time when 1(ns) is elapsed after the time Tu, it is necessary that the data signal DATA be settled. Unless otherwise, it is not possible to correctly carry out the data sampling. The above-described time 1.5(ns) is referred to as a data setup time tsu, and the time 1(ns) is referred to as a data hold time th.
FIGS. 20(a) and 20(b) show examples of time charts of the relation between the clock signal and 1 bit of the data. In FIG. 20(a), at the time that is 0.5(ns) to the rising of the clock signal, the 1 bit of the data falls down to xe2x80x9cLxe2x80x9d from xe2x80x9cHxe2x80x9d. In this case, since the data changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d within the data setup time tsu=1.5(ns), it is not possible to correctly carry out the data sampling.
In contrast, in FIG. 20(b), at the time that is 3(ns) to the rising of the clock signal, the 1 bit of the data falls down to xe2x80x9cLxe2x80x9d from xe2x80x9cHxe2x80x9d. In this case, since the data changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d prior to reaching the data setup time tsu=1.5(ns), the sampling is made to the xe2x80x9cLxe2x80x9d of the data.
As is clear from the foregoing description, when the sampling is carried out with respect to the data in synchronization with the rising of the clock signal, the time period in which the data can be changed, i.e., the data sampling margin is indicated by the oblique line shown in FIG. 21. Namely, the data sampling margin corresponds to the period between the time when time th (the data hold time th) is elapsed after the rising of the clock signal and the time that is tsu (the data setup time) to the rising of the next clock signal.
For example, when it is assumed that the duty ratio of the clock signal is 50 percent, since the clock period Tck is equal to 25(ns), the data sampling margin is 22.5(ns)(=Tckxe2x88x92tsuxe2x88x92th=25(ns)xe2x88x921.5(ns)xe2x88x921(ns)) in the case of SVGA. The data sampling margin is 12.88(ns)(=Tckxe2x88x92tsuxe2x88x92th=15.38(ns)xe2x88x921.5(ns)xe2x88x921(ns)) in the case of XGA because the clock period Tck is equal to 15.38(ns).
Further, in actual, it takes more time for the clock signal and the data signal to rise up or fall down and it is necessary to consider the time required for the data signal to fall down to a threshold voltage (for example, 0.3xc3x97VCC) so as to be recognized to be xe2x80x9cLxe2x80x9d or the data signal to rise up to a threshold voltage (for example, 0.7xc3x97VCC) so as to be recognized to be xe2x80x9cHxe2x80x9d. This results in that the time differences A and B when the time required for the above-mentioned rising and falling is not considered becomes longer the time differences Axe2x80x2 and Bxe2x80x2 when the time required for the above-mentioned rising and falling is considered (see FIG. 22). This causes the data sampling margin to be further reduced.
In order to increase the data sampling margin so as to address the deficiency, it may be contrived to make the risings and failings of the clock signal and the data signal faster, respectively. However, this causes each wave form of the signals to rapidly change, thereby resulting in that the higher harmonic wave components increase in the clock signal and the data signal. Accordingly, this invites that the EMI (Electromagnetic Interference) becomes worse.
Further, according to the structure shown in FIG. 18, the data signal DATA is connected in parallel with all the source drivers STAB1 through STAB8 via a single wiring. This causes to generate the wiring resistance and wiring capacity due to the wiring extending from the source driver STAB1 to STAB8. The wiring resistance and wiring capacity affect the data signal, more specifically, the data signal receives the affections such as the RC delay and the reflection. This causes the data signal to be sent to the source driver with being deviated from the originally inputted timing. This also causes the data sampling margin to be reduced.
As to the problem of the delay in the data signal due to the resistance across the wire and the capacity across the wire, the following method such as the self-transfer method or the data transfer method. According to the self-transfer method, when transferring the data signal from the timing controller to the respective source drivers, the source drivers are connected with each other in a cascade manner so as to carry out the data transfer. The following description deals with the data transfer based on the self-transfer method with reference to the structure disclosed in, for example, Japanese unexamined patent publication No. 10-153760 (publication date: Jun. 9, 1998).
FIG. 23 is a block diagram showing the schematic structure of the input-output sections with respect to a single basic clock signal CLK in the self-transfer method. As shown in FIG. 23, in response to a single basic clock signal CLK (1 bit), the control signals such as a data signal DATA (18 bits), an LS signal, and an SP signal are sent from a latch circuit 51 to a control logic section 52. Similarly, in response to the single basic clock signal CLK (1 bit), a data signal DATA (18 bits), an LS signal, and an SP signal are sent from a latch circuit 53 to the source driver of the next stage (not shown) that is connected with the previous source driver.
A clock cycle regulator 54 is constituted by a circuit for compensating the clock duty ratio such as a PLL and a DLL. Even when the clock signal is connected with each other in a multiple stage manner by the clock cycle regulator 54, the duty ratio of the clock signal is fixed, thereby ensuring to stably transfer the data.
However, the foregoing structure has the following problems. First, since the structure requires the clock cycle regulator 54, circuits to be required increase. This causes the size of the chip to become bulky. This raises the problems that the cost for the source driver becomes great and the size of the glass substrate becomes large due to the fact that the length of the short sides of the driver chip becomes long when carrying out the mounting based on the COG (Chip On Glass) mounting method.
For example, when adopting a module having the XGA resolution as the liquid crystal display apparatus, the frequency of the clock signal becomes 65 MHz according to the VESA standard. As described earlier, the data sampling margin becomes very severe. As the resolution further improves, the data sampling margin becomes more severe, accordingly. Under the circumstances, if it is intended to secure the data sampling margin by making the risings and failings of the clock signal and the data signal change rapidly, the problem of the EMI occurs as described earlier.
The present invention is made in view of the foregoing circumstances, and its object is to provide a signal transfer system, a display panel drive apparatus, and a display apparatus, each having a plurality of signal input-output sections that are connected with each other in a cascade manner in which the data sampling margin can be secured even when the transfer speed of the data signal is fast, and can suppress the affections of the EMI.
In order to achieve the object, a signal transfer system in accordance with the present invention is provided with a plurality of signal input-output sections that are connected with each other in a cascade manner, in which the signal input-output section of a first stage receives a plurality of signals and consecutively transfers the signals to the signal input-output sections of the following stages in accordance with self-transfer method, characterized in that wherein the signal input-output section includes: (a) first and second clock input sections that receive first and second clock signals, respectively, from the signal input-output section of a previous stage; (b) first and second clock output sections that invert and output the first and second clock signals to the signal input-output section of a next stage; (c) a data input section that receives a data signal from the signal input-output section of the previous stage in accordance with the first clock signal that has been inputted to the first clock input section; and (d) a data output section that outputs the data signal to the signal input-output section of the next stage in accordance with the second clock signal that has been inputted to the second clock input section.
With the arrangement, in each signal input-output section, the data signal is inputted to the data input section in accordance with the first clock signal and is outputted to the data output section in accordance with the second clock signal. This allows to output a stable data signal to the signal input-output section of the next stage even when the data signal, that has been inputted in accordance with the first clock signal, is easy to receive the affections such as the wiring capacity in the signal input-output section in the case where the data signal is transferred faster, because the data signal is outputted in accordance with the second clock signal. Thus, it is possible to guarantee the specification of the timing for fetching the data in the signal input-output section.
Since the first and second output sections invert and output the respective first and second clock signals to the signal input-output section of the next stage, the fluctuation of the duty ratio occurred when the first and second clock signals pass through each signal input-output section is canceled by the neighboring signal input-output sections. This allows to compensate the duty ratio of the clock signals in the multiple cascade connections, thereby enabling that the transfer system operates at a higher frequency.
Another signal transfer system in accordance with the present invention is provided with a plurality of signal input-output sections that are connected with each other in a cascade manner, in which the signal input-output section of a first stage receives a plurality of signals and consecutively transfers the signals to the signal input-output sections of the following stages in accordance with self-transfer method, characterized in that the signal input-output section includes: (a) first and second clock input sections that receive first and second clock signals, respectively, from the signal input-output section of a previous stage; (b) a data input section that receives a data signal from the signal input-output section of a previous stage in accordance with the first clock signal that has been inputted to the first clock input section; (c) a data output section that outputs the data signal to the signal input-output section of a next stage in accordance with the second clock signal that has been inputted to the second clock input section; (d) a first clock output section that outputs the second clock signal to the signal input-output section of the next stage as the first clock signal; and (e) a second clock output section that outputs the first clock signal to the signal input-output section of the next stage as the second clock signal.
With the arrangement, in each signal input-output section, the data signal is inputted to the data input section in accordance with the first clock signal and is outputted to the data output section in accordance with the second clock signal. This allows to output a stable data signal to the signal input-output section of the next stage even when the data signal, that has been inputted in accordance with the first clock signal, is easy to receive the affections such as the wiring capacity in the signal input-output section in the case where the data signal is transferred faster, because the data signal is outputted in accordance with the second clock signal. Thus, it is possible to guarantee the specification of the timing for fetching the data in the signal input-output section.
Since the first clock output section outputs the inputted second clock signal to the signal input-output section of the next stage as the first clock signal and the second clock output section outputs the first clock signal to the signal input-output section of the next stage as the second clock signal, it is possible to cancel the input-output delayed time difference between the first and second clock signals, when the continuing two signal input-output sections are regarded as one block. This allows to secure the data sampling margin and to make the transfer speed of the data signal faster.
A signal transfer apparatus, in accordance with the present invention, that is connected in a cascade manner so as to transfer a plurality of signals outputted from a signal transfer apparatus of a previous stage to a signal transfer apparatus of a next stage based on self-transfer method, characterized by further having: (a) first and second clock input sections that receive first and second clock signals, respectively, from the signal transfer apparatus of the previous stage; (b) first and second clock output sections that invert and output the first and second clock signals to the signal transfer apparatus of the next stage; (c) a data input section that receives a data signal from the previous stage in accordance with the first clock signal that has been inputted to the first clock input section; and (d) a data output section that outputs the data signal to the signal transfer apparatus of the next stage in accordance with the second clock signal that has been inputted to the second clock input section.
With the arrangement, the data signal is inputted to the data input section in accordance with the first clock signal and is outputted to the data output section in accordance with the second clock signal. This allows to output a stable data signal to the signal input-output section of the next stage even when the data signal, that has been inputted in accordance with the first clock signal, is easy to receive the affections such as the wiring capacity in the signal input-output section in the case where the data signal is transferred faster, because the data signal is outputted in accordance with the second clock signal. Thus, it is possible to guarantee the specification of the timing for fetching the data in the signal input-output section.
In addition thereto, the first and second clock output sections invert and output the first and second clock signals with respect to the respective next stages. This causes to cancel the fluctuation of the duty ratio occurred when the first and second clock signals pass through the signal transfer apparatus. This allows to compensate the duty ratio of the clock signals in the multiple cascade connections, thereby enabling that the transfer system operates at a higher frequency.
Another signal transfer apparatus in accordance with the present invention that is connected in a cascade manner so as to transfer a plurality of signals outputted from the signal transfer apparatus of a previous stage to the signal transfer apparatus of a next stage based on self-transferring, characterized by further having: (a) first and second clock input sections that receive first and second clock signals, respectively, from the signal transfer apparatus of a previous stage; (b) a data input section that receives a data signal from the signal transfer apparatus of a previous stage in accordance with the first clock signal that has been inputted to the first clock input section; (c) a data output section that outputs the data signal to the signal transfer apparatus of a next stage in accordance with the second clock signal that has been inputted to the second clock input section; (d) a first clock output section that outputs the second clock signal to the signal transfer apparatus of the next stage as the first clock signal; and (e) a second clock output section that outputs the first clock signal to the signal transfer apparatus of the next stage as the second clock signal.
With the arrangement, the data signal is inputted to the data input section in accordance with the first clock signal and is outputted to the data output section in accordance with the second clock signal. This allows to output a stable data signal to the signal transfer apparatus of the next stage even when the data signal, that has been inputted in accordance with the first clock signal, is easy to receive the affections such as the wiring capacity in the signal transfer apparatus in the case where the data signal is transferred faster, because the data signal is outputted in accordance with the second clock signal. Thus, it is possible to guarantee the specification of the timing for fetching the data in the signal transfer apparatus.
Since the first clock output section outputs the inputted second clock signal to the signal transfer apparatus of the next stage as the first clock signal and the second clock output section outputs the first clock signal to the signal transfer apparatus of the next stage as the second clock signal, it is possible to cancel the input-output delayed time difference between the first and second clock signals, when the continuing two signal transfer apparatuses are regarded as one block. This allows to secure the data sampling margin and to make the transfer speed of the data signal faster.
A display panel drive apparatus in accordance with the present invention for driving a display panel in which a plurality of pixels are provided and an electric signal is applied to each of the pixels so as to carry out a display, is provide with any one of the foregoing signal transfer system, and control logic section that receives the data signal from each signal input-output section of the signal transfer system and controls so as to output the electric signal to each pixel in the display panel in accordance with the data signal thus received.
With the arrangement, since the display panel is provided with a plurality of pixels, it is possible to appropriately transfer the data signal even when the data signal should be transferred at an extremely high speed. This allows to show the good display performance without display defect even to the display panel having many pixels.
According to the present invention, a display panel drive apparatus for driving a display panel in which a plurality of pixels are provided and an electric signal is applied to each of the pixels so as to carry out a display, is provided with the signal transfer apparatus and control logic section that receives the data signal from the signal transfer apparatus and controls so as to output the electric signal to each pixel in the display panel in accordance with the data signal thus received.
With the arrangement, since the display panel is provided with a plurality of pixels, it is possible to appropriately transfer the data signal even when the data signal should be transferred at an extremely high speed. This allows to show the good display performance without display defect even to the display panel having many pixels.
A display apparatus in accordance with the present invention is characterized by having: a display panel in which a plurality of pixels are provided and an electric signal is applied to each of the pixels so as to carry out a display; and any one of the display panel drive apparatus recited.
With the arrangement, since the display panel drive apparatus can transfer the data signal at a relatively high speed, it is possible to increase the number of the pixels of the display panel. Accordingly, it is possible to provide a display apparatus having an excellent display quality and enabling to carry out the high resolution display.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitative of the present invention.